1. Technical Field
Various embodiments generally relate to a data training device and a semiconductor device, and more particularly, to a technology capable of reflecting a training error due to a voltage drop in a semiconductor device.
2. Related Art
An operation speed and a degree of integration has been increased in order to improve semiconductor memory devices. In order to improve an operation speed, there has emerged a so-called synchronous memory device capable of operating in synchronization with a clock provided from an exterior.
A DDR (Double Data Rate) synchronous memory device processes two pieces of data in one clock cycle. Two pieces of data are continuously inputted/outputted through each data input/output pin in synchronization with a rising edge and a falling edge of a clock inputted from an exterior. Accordingly, it is possible to perform a high speed operation because it is possible to achieve twice the bandwidth without increasing a frequency of a clock as compared with a conventional SDR (Single Data Rate) synchronous memory device.
Furthermore, it is important to reduce current consumption in a low power DDR synchronous memory device operating at a low power supply voltage. To this end, the low power DDR synchronous memory device should operate an internal clock only during a required period in order to reduce an operation current.
That is, a conventional low power DDR synchronous memory device reduces an operation current needed by operating an internal clock only for an appropriate time by using a setup time of a chip select signal after a command is applied and disabling the internal clock in the other periods. In this case, only when the rising and is falling edges of the clock exist in a valid window of data DATA, a semiconductor memory device may accurately receive the data DATA.
However, as the operation frequency of a memory device gradually increases, a setup time and a hold time of the chip select signal are narrowly applied. In general, it is evaluated whether the operation performance of a semiconductor memory device is good as a write and read operation is performed at a high speed.
Particularly, a required data output time of a semiconductor memory device that processes a large amount of data, such as an image, is a very important performance index. In addition, as data outputted from a semiconductor memory device is accurately transferred, a system stably operates.
Recently, a semiconductor memory device and a GPU (Graphics Processing Unit) overcome the conventional problems through data training and perform high speed data transfer. The data training indicates a technology for adjusting a skew of data by using a training pattern promised in advance between a controller and the semiconductor memory device in order to stably transfer data for read and write operations.